1. Technical Field
Embodiments of the present invention relate generally to data processing. More particularly, embodiments relate to techniques for saving and/or retrieving context information of a processor core for a power state transition associated with the processor core.
2. Background Art
Processor devices on high-availability platforms, such as those used for Mobile Internet Device (MID) applications, must support “always-on” modes of operation. Always on modes of operation are generally characterized by low latency entry to and/or exit from very low power states on the platform while maintaining an operating system (OS) context and external connectivity. In order to reach very low power states from a platform perspective, most processor device blocks are typically powered off and state is typically retained either in hardware (HW) or by software (SW) interaction. Such processor device blocks can include one or more cores of a processor—e.g. a central processing unit (CPU) on the platform.
CPU context information is often retained in CPU cache—e.g. a L2 cache of a processor core which is dedicated to operate as a context storage SRAM. However, leakage associated with such volatile local CPU storage often makes it infeasible to retain this state during low power modes. However, not retaining CPU context information in HW has an adverse effect on exit from these low power states. Alternatives to HW typically require SW to save and restore architectural and/or micro-architectural state, which increases exit latency. Since processor core state restoration operates at a much higher power level than standby, an increase of 1 ms in serialized exit latency can decrease battery life, e.g. by ˜8%, in some circumstances.